Tensilica Instruction Extension - TIE Testing & Verification

TIE Testing & Verification

Once the code has been compiled using the TIE compiler, there are minimum two levels of verification & testing required to verify the functionality.

  1. Software Testing: Using the intrinsic interfaces of TIE operations from C/C++, the TIEs are first integrated with the C code that tests the required application functionality. After such integration, testing of the software running on the Xtensa core is performed by using the software simulator on PC (The Xtensa simulator on PC is called Instruction Set Simulator - ISS).
  2. Hardware Verification: The TIE compiler's output RTL and Netlists are given as input to various simulators like Modelsim. the required functionality of the TIE is verified by hardware simulation. Such verification requires a Hardware/Software co-simulation environment to be prepared, where the required software can be tested for its functionality.

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