Scan chain is a technique used in design for testing. The objective is to make testing easier by providing a simple way to set and observe every flip-flop in an IC.The basic structure of scan include the following set of signals in order to control and observe the scan mechanism.
- Scan_in_and_scan_out define the input and output of a scan chain. In a full scan mode usually each input drives only one chain and scan out observe one as well .
- A scan enable pin is a special signal that is added to a design. When this signal is asserted, every flip-flop in the design is connected into a long shift register.
- Clock signal which is used for controlling all the FFs in the chain during shift phase and the capture phase. An arbitrary pattern can be entered into the chain of flip-flops, and the state of every flip-flop can be read out.
In a full scan design, automatic test pattern generation is particularly simple. No sequential pattern generation is required - combinatorial tests, which are much easier to generate, will suffice. If you have a combinatorial test, it can be easily applied.
- Assert scan mode, and set up the desired inputs.
- De-assert scan mode, and apply one clock. Now the results of the test are captured in the target flip-flops.
- Re-assert scan mode, and see if the combinatorial test passed.
In a chip that does not have a full scan design -- i.e., the chip has sequential circuits, such as memory elements that are not part of the scan chain, sequential pattern generation is required. Test pattern generation for sequential circuits searches for a sequence of vectors to detect a particular fault through the space of all possible vector sequences.
Even a simple stuck-at fault requires a sequence of vectors for detection in a sequential circuit. Also, due to the presence of memory elements, the controllability and observability of the internal signals in a sequential circuit are in general much more difficult than those in a combinational logic circuit. These factors make the complexity of sequential ATPG much higher than that of combinational ATPG.
There are many variants:
- Partial scan: Only some of the flip-flops are connected into chains.
- Multiple scan chains: Two or more scan chains are built in parallel, to reduce the time to load and observe.
- Test compression: the input to the scan chain is provided by on-board logic
Read more about Scan Chain: See Also
Other articles related to "scan, scan chain, chain":
... area.) One of those other TAPs will handle boundary scan testing for the whole chip it is not supported by the debug TAP ... of such chips include The OMAP2420, which includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine ... similar, although its "System JTAG" boundary scan TAP, which is very different from ICEpick, and it includes a TAP for its DMA engine instead of a DSP and imaging engine ...
... logic are linked together in a set called the Boundary Scan chain ... When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults (sh ... The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur ...
... chip select line), protocol messages, a core command set, the ability to daisy-chain devices in a "scan chain", and how vendors define new commands ... The devices in a scan chain are initially treated as a single device, and transitions on TMS update their state machines once the individual devices are identified, commands may ... used in JTAG are often long and not multiples of 8 bit words for example, a boundary scan reports signal state on each of several hundred pins ...
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