NAND Flash Memory Makers
Similar to the multiple patterning approach described for Intel's 11 nm process, in actual practice, NAND Flash memory array patterning using the spacer approach would use 3 or more mask exposures. The first mask patterns the array core by defining the spacers, while a second mask is used to crop or trim the spacers to form individual lines. Lastly, additional masks or multiple patterning would be used to pattern peripheral connections, e.g., pads. As a result, Flash memory patterning can generally be considered multiple patterning, not just a spacer-based double-patterning technique.
At IEDM 2011, Hynix is expected to report on a 15 nm NAND process, making use of, among other things, quadruple spacer patterning.
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—John Ruskin (18191900)
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—Ralph Waldo Emerson (18031882)
“We cannot know how much we learn
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Until a flash of unforeseen
Remembrance falls on what has been.”
—Edwin Arlington Robinson (18691935)