MIPS Architecture - CPU Family

CPU Family

The first commercial MIPS model, the R2000, was announced in 1985. It added multiple-cycle multiply and divide instructions in a somewhat independent on-chip unit. New instructions were added to retrieve the results from this unit back to the register file; these result-retrieving instructions were interlocked.

The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register (the designers considered it a potential bottleneck), a feature it shares with the AMD 29000 and the Alpha. Unlike other registers, the program counter is not directly accessible.

The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision.

The R3000 succeeded the R2000 in 1988, adding 32 KB (soon increased to 64 KB) caches for instructions and data, along with cache coherency support for multiprocessor use. While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in MMU, a common feature on CPUs of the era. The R3000, like the R2000, could be paired with a R3010 FPU. The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made. A speed-bumped version of the R3000 running up to 40 MHz, the R3000A delivered a performance of 32 VUPs (VAX Unit of Performance). The MIPS R3000A-compatible R3051 running at 33.8688 MHz was the processor used in the Sony PlayStation. Third-party designs include Performance Semiconductor's R3400 and IDT's R3500, both of them were R3000As with an integrated R3010 FPU. Toshiba's R3900 was a virtually first SoC for the early handheld PCs that ran Windows CE. A radiation-hardened variant for space applications, the Mongoose-V, is a R3000 with an integrated R3010 FPU.

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and they took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). The improved R4400 followed in 1993. It had larger 16 KB primary caches, largely bug-free 64-bit operation, and support for a larger L2 cache.

MIPS, now a division of SGI called MTI, designed the low-cost R4200, the basis for the even cheaper R4300i. A derivative of this microprocessor, the NEC VR4300, was used in the Nintendo 64 game console.

Quantum Effect Devices (QED), a separate company started by former MIPS employees, designed the R4600 Orion, the R4700 Orion, the R4650 and the R5000. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the SGI Indy workstation as well as the first MIPS based Cisco routers, such as the 36x0 and 7x00-series routers. The R4650 was used in the original WebTV set-top boxes (now Microsoft TV). The R5000 FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked R4400 Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with R5000 in order to emphasize the improvement. QED later designed the RM7000 and RM9000 family of devices for embedded markets like networking and laser printers. QED was acquired by the semiconductor manufacturer PMC-Sierra in August 2000, the latter company continuing to invest in the MIPS architecture. The RM7000 included an on-board 256 KB level 2 cache and a controller for optional level three cache. The RM9xx0 were a family of SOC devices which included northbridge peripherals such as memory controller, PCI controller, gigabit ethernet controller and fast IO such as a hypertransport port.

The R8000 (1994) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's POWER Challenge servers in the mid 1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare.

In 1995, the R10000 was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.

Later designs have all been based upon R10000 core. The R12000 used a 0.25 micrometre process to shrink the chip and achieve higher clock rates. The revised R14000 allowed higher clock rates with additional support for DDR SRAM in the off-chip cache. Later iterations are named the R16000 and the R16000A and feature increased clock speed and smaller die manufacturing compared with before.

Other members of the MIPS family include the R6000, an ECL implementation produced by Bipolar Integrated Technology. The R6000 introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market.

MIPS Microprocessors
Model Frequency (MHz) Year Process (nm) Transistors (millions) Die Size (mm2) Pin Count Power (W) Voltage (V) D. cache (KB) I. cache (KB) L2 Cache L3 Cache
R2000 8–16.67 1985 2000 0.11 ? ? ? ? 32 64 None None
R3000 12–40 1988 1200 0.11 66.12 145 4 ? 64 64 0–256 KB External None
R4000 100 1991 800 1.35 213 179 15 5 8 8 1 MB External None
R4400 100–250 1992 600 2.3 186 179 15 5 16 16 1-4 MB External None
R4600 100–133 1994 640 2.2 77 179 4.6 5 16 16 512 KB External None
R4650 133–180 1994 640 2.2? 77? 179 4.6? 5 16 16 512 KB External None
R4700 100–200 1996 500 2.2? ? 179 ? ? 16 16 External none
R5000 150–200 1996 350 3.7 84 223 10 3.3 32 32 1 MB External None
R8000 75–90 1994 700 2.6 299 591+591 30 3.3 16 16 4 MB External None
R10000 150–250 1996 350, 250 6.7 299 599 30 3.3 32 32 512 KB–16 MB external None
R12000 270–400 1998 250, 180 6.9 204 600 20 4 32 32 512 KB–16 MB external None
RM7000 250–600 1998 250, 180, 130 18 91 304 10, 6, 3 3.3, 2.5, 1.5 16 16 256 KB internal 1 MB external
MIPS32 4K 1999
MIPS64 5K 1999
MIPS64 20K 2000
R14000 500–600 2001 130 7.2 204 527 17 ? 32 32 512 KB–16 MB external None
R16000 700–1000 2002 110 ? ? ? 20 ? 32 32 512 KB–16 MB external None
MIPS32 24K 400 (130 nm)
750 (65 nm)
1468 (40 nm)
2003 40–130 ? 0.83 ? ? ? 64 64 4–16 MB external None
MIPS32 34K 500 (90 nm)
1454 (40 nm)
2006 90, 65, 40
MIPS32 74K 1080 2007 65
MIPS32 1004K 1100 2008 65
MIPS32 1074K 1500 2010 40
MIPS32 microAptiv 2012
MIPS32 interAptiv 2012
MIPS32 proAptiv 2012

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