CAS Latency

CAS Latency

Column Address Strobe (CAS) latency, or CL, is the delay time between the moment a memory controller tells the memory module to access a particular memory column on a RAM memory module, and the moment the data from the given array location is available on the module's output pins. In general, the lower the CAS latency, the better.

In asynchronous DRAM, the interval is specified in nanoseconds. In synchronous DRAM, the interval is specified in clock cycles. Because the latency is dependent upon a number of clock ticks instead of an arbitrary time, the actual time for an SDRAM module to respond to a CAS event might vary between uses of the same module if the clock rate differs.

Read more about CAS LatencyRAM Operation Background, Effect On Memory Access Speed

Other articles related to "cas latency":

SDRAM Timing
... Another limit is the CAS latency, the time between supplying a column address and receiving the corresponding data ... In operation, CAS latency is a specific number of clock cycles programmed into the SDRAM's mode register and expected by the DRAM controller ... At higher clock rates, the useful CAS latency in clock cycles naturally increases ...
CAS Latency - Effect On Memory Access Speed - Memory Timing Examples
... Memory timing examples (CAS latency only) Generation Type Data rate Bit time Command rate Cycle time CL First word Fourth word Eighth word SDRAM PC100 100 MT/s  10 ns ...