Compiler Code Generation
Conte has also made significant contributions to profile-driven optimization. He was the first to realize that the limit to profile-driven optimization wasn’t the technology itself, but it was the slowdown due to profiling that prevented its adoption by industry. He and his students devised clever techniques to extract profile information from branch predictors on Intel Pentium processor. He then went on to prescribe new design criteria for microprocessor performance monitoring hardware to make such hardware useful to a compiler. The results are reflected in the performance counters that are present in the Intel Itanium, co-designed by one of Conte’s Ph.D. students (Kishore Menezes). In compiler code generation, Conte developed Treegion Scheduling, a novel technique for code scheduling that is used today in VLIW DSP compilers. The technique can produce performance similar to Scott Mahlke’s hyperblock scheduling, but without needing predication support in the hardware. He and his students also invented a technique for scheduling code in the presence of distributed register files (as are common in DSPs), optimizing code for both run time efficiency and code size efficiency (as is critical for embedded code), and exploiting value locality in code generation of EPIC architectures.
Read more about this topic: Tom Conte, Academic Contributions
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