Successive Approximation ADC - Charge-redistribution Successive Approximation ADC - Use With Non-ideal Analog Circuits

Use With Non-ideal Analog Circuits

When implemented as an analog circuit - where the value of each successive bit is not perfectly 2^N (e.g. 1.1, 2.12, 4.05, 8.01, etc.) - a successive approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending on the difference between actual and ideal performance, the maximum error can easily exceed several LSBs, especially as the error between the actual and ideal 2^N becomes large for one or more bits. Since we don't know the actual unknown input, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be very close to the ideal 2^N values; otherwise, we cannot guarantee a best match search.

ADVANTAGES 1] The conversion time is equal to the "n" clock cycle period for an n-bit ADC. Thus conversion time is very short. For example for a 10-bit ADC with a clock frequency of -1 MHz,the conversion time will be 10*10^-6 i.e. 10 micro sec. only. 2]Conversion time is constant and independent of the amplitude of analog signal V to the base A