ONFI has produced a specification for a standard interface to NAND flash chips.
Version 1.0 of this specification was released on December 28, 2006, and is available at no cost from the ONFI web site (see External links). It specifies:
- a standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
- a standard mechanism for NAND chips to identify themselves and describe their capabilities (comparable to the Serial Presence Detection feature of SDRAM modules)
- a standard command set for reading, writing, and erasing NAND flash
- standard timing requirements for NAND flash
- improved performance via a standard implementation of read cache and increased concurrency for NAND flash operations
- improved data integrity by allowing optional ECC memory features
Version 2.0 - February 2008 ONFI 2.0 defines a high-speed NAND Flash interface that can deliver speeds greater than 133 MB/s, whereas the legacy NAND interface was limited to 50 MB/s.
Version 2.1 - January 2009 New features that deliver speeds of 166 MB/s and 200 MB/s, plus other enhancements to increase power, performance, and ECC capabilities.
Version 2.2 - October 2009 - Individual LUN reset - Enhanced program page register clear - New Icc specs and measurement LUN reset and page register clear enable more efficient operation in larger systems with many NAND devices, while the standardized Icc testing and definitions will provide simplified vendor testing and improved data consistency
Block Abstracted NAND: ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface. The ONFI Workgroup continues to evolve the ONFI specifications to meet the needs of a rapidly growing and changing industry.
NAND Connector: The NAND Connector Specification was ratified in April 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and SSDs in PC platforms.
Version 3.0 - March 2011 - promotes a high-speed NAND Flash interface supporting transfer rates up to 400 MB/s - requires fewer chip-enable pins enabling more efficient PCB routing - designed for the future and supports the EZ-NAND interface
Read more about this topic: Open NAND Flash Interface Working Group
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