Interrupts in 65xx Processors - Interrupt Types

Interrupt Types

65xx interrupt vector locations
Interrupt Vector (hexadecimal)
LSB MSB
ABORT FFF8 FFF9
COP FFF4 FFF5
NMI FFFA FFFB
RESET FFFC FFFD
IRQ/BRK FFFE FFFF

The hardware interrupt signals are all active low, and are as follows:

RESET
a reset signal, level-triggered
NMI
a non-maskable interrupt, edge-triggered
IRQ
a maskable interrupt, level-triggered
ABORT
a special-purpose, non-maskable interrupt (65C816 only, see below), level-triggered

The detection of a RESET signal causes the processor to enter a system initialization period of six clock cycles, after which it sets the interrupt request disable flag in the status register and loads the program counter with the values stored at the processor initialization vector ($FFFC-$FFFD) before commencing execution.

65C816/65C802 "native mode" interrupt vector locations
Interrupt Vector (hexadecimal)
LSB MSB
ABORT 00FFE8 00FFE9
COP 00FFE4 00FFE5
BRK 00FFE6 00FFE7
NMI 00FFEA 00FFEB
RESET None
IRQ 00FFEE 00FFEF

The detection of an NMI or IRQ signal, as well as the execution of a BRK instruction, will cause the same overall sequence of events, which are, in order:

  1. The processor completes the current instruction and updates registers or memory as required before responding to the interrupt.
  2. The program bank register (PB, the A16-A23 part of the address bus) is pushed onto the hardware stack (65C816/65C802 only when operating in native mode).
  3. The most significant byte (MSB) of the program counter (PC) is pushed onto the stack.
  4. The least significant byte (LSB) of the program counter is pushed onto the stack.
  5. The status register (SR) is pushed onto the stack.
  6. The interrupt disable flag is set in the status register.
  7. PB is loaded with $00 (65C816/65C802 only when operating in native mode).
  8. PC is loaded from the relevant vector (see tables).

The behavior of the 65C816 when ABORT is asserted differs in some respects from the above description and is separately discussed below.

Note that the processor does not push the accumulator and index registers on to the stack—code in the interrupt handler must perform that task, as well as restore the registers at the termination of interrupt processing, as necessary. Also note that the vector for IRQ is the same as that for BRK in all eight bit 65xx processors, as well as in the 65C802/65C816 when operating in emulation mode. When operating in native mode, the 65C802/65C816 provide separate vectors for IRQ and BRK.

When set, the interrupt request disable flag (the I bit in the status register) will disable detection of the IRQ signal, but will have no effect on any other interrupts (however, see below section on the WAI instruction implemented in WDC CMOS processors). Additionally, with the 65(c)02 or the 65C816/65C802 operating in emulation mode, the copy of the status register that is pushed on to the stack will have the B flag set if a BRK (software interrupt) was the cause of the interrupt, or cleared if an IRQ was the cause. Hence the interrupt service routine must retrieve a copy of the saved status register from where it was pushed onto the stack and check the status of the B flag in order to distinguish between an IRQ and a BRK. This requirement is eliminated when operating the 65C802/65C816 in native mode, due to the separate vectors for the two interrupt types.

Read more about this topic:  Interrupts In 65xx Processors

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