DDR4 SDRAM - Technical Description - Command Encoding

Command Encoding

Although it still operates in fundamentally the same way, DDR4 makes one major change to the command formats used by previous SDRAM generations. A new command signal /ACT is low to indicate the activate (open row) command.

The activate command requires more address bits than any other (18 row address bits in an 8 Gb part), so the standard /RAS, /CAS and /WE signals are shared with high-order address bits that are not used when /ACT is high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate command is unused.

As in previous SDRAM encodings, A10 is used to select command variants: auto-precharge on read and write commands, and one bank vs all banks for the precharge command. It also selects two variants of the ZQ calibration command.

In addition, A12 is used to request burst chop: truncation of an 8-transfer burst after 4 transfers. Although the bank is still busy and unavailable for other commands until 8 transfer times have elapsed, a different bank can be accessed.

Also, the number of bank addresses has been increased greatly. There are 4 bank select bits to select up to 16 banks within each DRAM: 2 bank address bits (BA0, BA1), and 2 bank group bits (BG0, BG1). There are additional timing restrictions when accessing banks within the same bank group; it is faster to access a bank in a different bank group.

In addition, there are 3 chip select signals (C0, C1, C2), allowing up to 8 stacked chips to be placed inside a single DRAM package. These effectively act as three more bank select bits, bringing the total to 7 (128 possible banks).

DDR4 command encoding
/CS BGn, BAn /ACT A17 A16
A13 A12 A11 A10 A9–0 Command
H — x — Deselect (No operation)
L bank L Row address Active (activate): open a row
L x H x H H H — x — No operation
L x H x H H L x long x ZQ Calibration
L bank H x H L H x BC x AP  Column  Read (BC=burst chop)
L bank H x H L L x BC x AP Column Write (AP=auto-precharge)
L x H x L H H — x — (Unassigned, reserved)
L x H x L H L x H x Precharge all banks
L bank H x L H L x L x Precharge one bank
L x H x L L H — x — Refresh
L register H 0 L L L 0 data Mode register set (MR0–MR6)

Note: x bits are "don't care", but must be at a valid voltage level, either 0 or 1.

Standard transfer rates are 1600, 1866, 2133 and 2400 MT/s. (12/15, 14/15, 16/15 and 18/15 GHz clock speeds, double data rate.) 2666 and 3200 MT/s (20/15 and 24/15 GHz clock speeds) are provided for, but the specifications are not yet complete.

Read more about this topic:  DDR4 SDRAM, Technical Description

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