VHDL-AMS

VHDL-AMS is a derivative of the hardware description language VHDL (IEEE standard 1076-1993). It includes analog and mixed-signal extensions (AMS) in order to define the behavior of analog and mixed-signal systems (IEEE 1076.1-1999).

The VHDL-AMS standard was created with the intent of enabling designers of analog and mixed signal systems and integrated circuits to create and use modules that encapsulate high-level behavioral descriptions as well as structural descriptions of systems and components.

VHDL-AMS is an industry standard modeling language for mixed signal circuits. It provides both continuous-time and event-driven modeling semantics, and so is suitable for analog, digital, and mixed analog/digital circuits. It is particularly well suited for verification of very complex analog, mixed-signal and radio frequency integrated circuits.

Read more about VHDL-AMS:  Code Example

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VHDL-AMS - Code Example
... In VHDL-AMS, a design consists at a minimum of an entity which describes the interface and an architecture which contains the actual implementation ... A simple ideal diode in VHDL-AMS would look something like this -- (this is a VHDL comment) library IEEE use IEEE.math_real.all use IEEE.electrical_systems.all -- this is the entity entity DIODE is generic (iss ...