Cache Line

Some articles on cache line, cache, cache lines, caches:

CPU Cache - Overview - Cache Performance - CPU Stalls
... The time taken to fetch one cache line from memory (read latency) matters because the CPU will run out of things to do while waiting for the cache line ... As CPUs become faster, stalls due to cache misses displace more potential computation modern CPUs can execute hundreds of instructions in the time taken to fetch a single cache line from main memory ... after the instruction that is waiting for the cache miss data ...
SDR SDRAM - SDRAM Burst Ordering
... A modern microprocessor with a cache will generally access memory in units of cache lines ... To transfer a 64-byte cache line requires 8 consecutive accesses to a 64-bit DIMM, which can all be triggered by a single read or write command by ... A cache line fetch is typically triggered by a read from a particular address, and SDRAM allows the "critical word" of the cache line to be transferred first ...
Bus Sniffing
... technique used in distributed shared memory systems and multiprocessors to achieve cache coherence ... Although there is one main memory, there are several caches (one per processor), and unless preventative steps are taken, the same memory location may be loaded into ... To prevent this, every cache controller monitors the bus, listening for broadcasts which may cause it to invalidate its cache line ...
Cache Coherency - Cache Coherence Mechanisms
... in a common directory that maintains the coherence between caches ... which the processor must ask permission to load an entry from the primary memory to its cache ... When an entry is changed the directory either updates or invalidates the other caches with that entry ...

Famous quotes containing the word line:

    This wild night, gathering the washing as if it were flowers
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    slapping my face lightly, soundless merriment
    in the gesticulations of shirtsleeves ...
    Denise Levertov (b. 1923)