# Successive Approximation ADC - Algorithm

Algorithm

The successive approximation Analog to digital converter circuit typically consists of four chief subcircuits:

1. A sample and hold circuit to acquire the input voltage (Vin).
2. An analog voltage comparator that compares Vin to the output of the internal DAC and outputs the result of the comparison to the successive approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an approximate digital code of Vin to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog voltage equivalent of the digital code output of the SAR for comparison with Vin.

The successive approximation register is initialized so that the most significant bit (MSB) is equal to a digital 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code (Vref/2) into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit; otherwise, the bit is left a 1. Then the next bit is set to 1 and the same test is done, continuing this binary search until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the DAC at the end of the conversion (EOC).

Mathematically, let Vin = xVref, so x in is the normalized input voltage. The objective is to approximately digitize x to an accuracy of 1/2n. The algorithm proceeds as follows:

1. Initial approximation x0 = 0.
2. ith approximation xi = xi-1 - s(xi-1 - x)/2i.

where, s(x) is the signum-function(sgn(x)) (+1 for x ≥ 0, -1 for x < 0). It follows using mathematical induction that |xn - x| ≤ 1/2n.

As shown in the above algorithm, a SAR ADC requires:

1. An input voltage source Vin.
2. A reference voltage source Vref to normalize the input.
3. A DAC to convert the ith approximation xi to a voltage.
4. A Comparator to perform the function s(xi - x) by comparing the DAC's voltage with the input voltage.
5. A Register to store the output of the comparator and apply xi-1 - s(xi-1 - x)/2i.