Instruction Set
The AEA instruction format consisted of 5-bit instruction code, index bit and a 12-bit address.
The computer had 27 instructions:
ADD: The contents of memory location are added to Accumulator A. The contents of the memory location remain unchanged.
ADZ (Add and Zero): The contents of memory are added to Accumulator A. The contents of memory are set to zero.
SUB (Subtract): The contents of memory are subtracted from Accumulator A. The contents of memory remain unchanged.
SUZ (Subtract and Zero): The contents of memory are subtracted from Accumulator A. The contents of memory are set to zero.
MPY (Multiply): The contents of Accumulator A are multiplied by the contents of memory. The most significant part of the product is placed in the Accumulator A, the least significant part is placed in Register Q.
MPR (Multiply and Round): Identical to MPY instruction, the most significant part of the product in Accumulator A is rounded by adding one to the contents of Accumulator A if bit 1 of Q Register equals one.
MPZ (Multiply and Zero): Identical to MPR instruction, the contents of memory are set to zero.
DVP (Divide): The contents of Accumulator A and Register Q that form a dividend are divided by the contents of memory. The quotient is placed in Accumulator A and rounded unless the roundind would cause overflow.
COM (Complement Accumulator): The contents of Accumulator A are replaced with their two's complement. If the contents of the Accumulator A are positive, zero or minus one, the contents remain unchanged.
CLA (Clear and Add): The Accumulator A is loaded from memory. The contents of memory remain unchanged.
CLZ (Clear, Add and Zero): Similar to CLA instruction; the contents of memory are set to zero.
LDQ (Load Q Register): The Q Register is loaded with contents of memory. The contents of memory remain unchanged.
STO (Store Accumulator): The contents of Accumulator A are stored in memory. The contents of Accumulator A remain unchanged.
STQ (Store Q Register): The contents of Q Register are stored in memory. The contents of Q Register remain unchanged.
ALS N (Arithmetic Left Shift): The contents of Accumulator A are shifted left N places.
LLS N (Long Left Shift): The contents of Accumulator A and bits 1 - 17 of Q Register are shifted left as one register N places. The sign of Q Register is made to agree with sign of Accumulator A.
LRS N (Long Right Shift): Similar to LLS, but the contents are shifted right N places.
TRA (Transfer): The next instruction is taken from memory.
TSQ (Transfer and Set Q): The contents of the Q Register are replaced with an address field set to one greater than the location of the TSQ instruction. Next instruction is taken from memory.
TMI (Transfer on Minus Accumulator): The next instruction is taken from memory if the contents of the Accumulator A are negative. Otherwise the next instruction is taken in sequence.
TOV (Transfer on Overflow): If the overflow indicator is set, the next instruction is taken from memory.
AXT N (Address to Index): The Index Register is set to N.
TIX (Test Index and Transfer): If the Index Register is positive, it is decremented by one and the next instruction is taken from memory.
DLY (Delay): Execution stops until a timing signal is received. The next instruction is taken from memory.
INP (Input): The contents of input register specified by address are placed in Accumulator A. The input register is either set to zero or remains unchanged (depending upon the selected register).
OUT (Output): The contents of the Accumulator A are placed in output register specified by address.
Read more about this topic: Apollo Abort Guidance System, Description
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