VMEbus - Description


In many ways the VMEbus is equivalent or analogous to the pins of the 68000 run out onto a backplane. In many cases this could be considered a bad design. One is in theory limited to chipset buses similar to the 68000.

However, one of the key features of the 68000 was a flat 32-bit memory model, free of memory segmentation and other "anti-features". The result is that, while VME is very 68000-like, the 68000 is generic enough to make this not an issue in most cases.

Like the 68000, VME uses separate 32-bit data and address buses. The 68000 address bus was actually 24-bit and the data bus 16-bit (although it was 32/32 internally) but the designers were already looking towards a full 32-bit implementations.

In order to allow both bus widths, VME uses two different Eurocard connectors - P1 and P2. P1 contains three rows of 32 pins each, implementing the first 24 address bits, 16 data bits and all of the control signals. P2 contains one more row, which includes the remaining 8 address bits and 16 data bits.

The bus is controlled by a set of nine lines, known as the arbitration bus. All communications are controlled by the card in slot one of the Eurocard chassis, known as the arbiter module. Two arbitration modes are supported - Round Robin and Prioritized.

Regardless of the arbitration mode, a card can attempt to become the bus master by holding one of the four Bus Request lines low. With round robin arbitration, the arbiter cycles amongst Bus Request lines BR0-BR3 to determine which of the potentially simultaneous requesters will be granted the bus. With priority arbitration, BR0-BR3 use a fixed priority scheme (BR0 lowest, up to BR3 highest) and the arbiter will grant the bus to the highest priority requestor.

When the arbiter has determined which of the bus requests to grant, it asserts the corresponding Bus Grant line (BG0 - BG3) for the level that won bus mastership. If two masters simultaneously request the bus using the same BR line, a bus grant daisy-chain effectively breaks the tie by granting the bus to the module closest to the arbiter. The master granted the bus will then indicate that the bus is in use by asserting Bus Busy (BBSY*).

At this point, the master has gained access to the bus. To write data, the card drives an address, an address modifier and data onto the bus. It then drives the address strobe line and the two data strobe lines low, to indicate the data is ready, and drives the write pin to indicate the transfer direction. There are two data strobes and an *LWORD line, so the cards can indicate if the data width is 8, 16, or 32 bits (or 64 in VME64). The card at the bus address reads the data and pulls the data transfer acknowledge low line when the transfer can complete. If the transfer cannot complete, it can pull the bus error line low. Reading data is essentially the same but the controlling card drives the address bus, leaves the data bus tri-stated and drives the read pin. The slave card drives read data onto the data bus and drives the data strobe pins low when the data is ready. The signalling scheme is asynchronous, meaning that the transfer is not tied to the timing of a bus clock pin (unlike synchronous buses such as PCI).

A block transfer protocol allows several bus transfers to occur with a single address cycle. In block transfer mode, the first transfer includes an address cycle and subsequent transfers require only data cycles. The slave is responsible for ensuring that these transfers use successive addresses.

Bus masters can release the bus in two ways. With Release When Done (RWD), the master releases the bus when it completes a transfer and must re-arbitrate for the bus before every subsequent transfer. With Release On Request (ROR), the master retains the bus by continuing to assert BBSY* between transfers. ROR allows the master to retain control over the bus until a Bus Clear (BCLR*) is asserted by another master that wishes to arbitrate for the bus. Thus a master which generates bursts of traffic can optimize its performance by arbitrating for the bus on only the first transfer of each burst. This decrease in transfer latency comes at the cost of somewhat higher transfer latency for other masters.

Address modifiers are used to divide the VME bus address space into several distinct sub-spaces. The address modifier is a 6 bit wide set of signals on the backplane. Address modifiers specify the number of significant address bits, the privilege mode (to allow processors to distinguish between bus accesses by user level or system level software), and whether or not the transfer is a block transfer. Below is an incomplete table of address modifiers:

Hex Code Function Explanation
3f Standard Supervisory block transfer Block transfer A24, privileged
3e Standard Supervisory Program access A24 instruction access, privileged
3d Standard Supervisor Data Access A24 data access, privileged
3b Standard Non-privileged block transfer A24 block transfer for normal programs
3a Standard Non-privileged Program access A24 instruction access, non-privileged
39 Standard non-privileged Data Access A24 data access, non-privileged
2d Short supervisory Access A16 privileged access.
29 Short non-privileged Access A16 non-privileged access.
0f Extended supervisory Block transfer A32 privileged block transfer.
0e Extended supervisory Program access A32 privileged instruction access.
0d Extended supervisory Data Access. A32 privileged data access.
0b Extended Non-privileged Block transfer A32 non-privileged block transfer.
0a Extended Non-privileged Program access A32 non-privileged instruction access.
09 Extended non-privileged data access. A32 non-privileged data access.
Note An as in A16, A24, A32 refers to the width of the address

VME also decodes all seven of the 68000's interrupt levels onto a 7-pin interrupt bus. The interrupt scheme is one of prioritized vectored interrupts. The interrupt request lines (IRQ1 - IRQ7) prioritize interrupts. An interrupting module asserts one of the interrupt request lines. Any module on the bus may potentially handle any interrupt. When an interrupt handling module recognizes an interrupt request at a priority it handles, it arbitrates for the bus in the usual fashion described above. It then performs a read of the interrupt vector by driving the binary version of the IRQ line it handles (e.g. if IRQ5 is being handled, then binary 101) onto the address bus. It also asserts the IACK line, along with the appropriate data transfer strobes for the width of the status/ID being read. Again, LWORD*, DS0* and DS1* allow status/ID read cycles to be 8, 16, or 32 bit wide transfers but most existing hardware interrupters use 8 bit status/IDs. The interrupter responds by transferring a status/ID on the data bus to describe the interrupt. The interrupt handling module (usually a CPU) will usually use this status/ID number to identify and run the appropriate software interrupt service routine.

On the VME bus, all transfers are DMA and every card is a master or slave. In most bus standards, there is a considerable amount of complexity added in order to support various transfer types and master/slave selection. For instance, with the ISA bus, both of these features had to be added alongside the existing "channels" model, whereby all communications was handled by the host CPU. This makes VME considerably simpler at a conceptual level while being more powerful, though it requires more complex controllers on each card.

Read more about this topic:  VMEbus

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