VIA Nano - Architecture Improvements

Architecture Improvements

  • Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with current offerings from AMD and Intel, except for Intel Atom which has an in-order design.
  • Instructions fusion: Allows the processor to combine some instructions as a single instruction, reducing power requirements and giving higher performance (the Atom uses a similar strategy in processing x86 instructions in a more 'whole' manner, rather than breaking them into RISC-like micro-ops).
  • Improved branch prediction: Uses eight predictors in two pipeline stages.
  • CPU cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
  • Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
    • Fetches 4 x86 instructions per cycle as opposed to Intel's 3-5
    • Issues 3 micro-operations/clock to execution units
  • Memory access: Merging of smaller stores into larger load data.
  • Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
    • 2 Integer units
      • One unit (ALU1) is feature complete, while the other (ALU2) lacks some low usage instructions and therefore can be used more often for tasks like address calculations.
    • 2 Store units (VIA refer to this as one for Address Store and another for Data Store)
    • 1 Load unit
    • 2 Media units with 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations.
      • One unit (MEDIA-A) correspond to floating point support, 2-clock latency for single-precision and double-precision add instructions, integer SIMD, encryption, divide and square root.
      • The other unit (MEDIA-B) performs single-precision multiplies, with 3-clock latency for double-precision multiplies.
  • Media computation: Refers to the use of floating point execution units.
    • Using an execution unit for floating point computation and another for multiplication allows the execution of up to four floating point and four multiplies per clock.
    • A new implementation of FP-addition with the lowest latency (in clocks) seen in x86 processors so far.
    • Almost all integer SIMD instructions execute in one clock.
    • Implements MMX, SSE, SSE2, SSE3, SSSE3 multimedia instruction sets
    • Implements SSE4 multimedia instruction set (VIA Nano 3000 series)
    • Implements SSE4.1 multimedia instruction set (VIA Nano x2 series)
  • Power Management: Besides requiring very low power, many new features are included.
    • Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
    • Adaptive P-State Control: Transition between performance and voltage states without stopping execution.
    • Adaptive Overclocking: Automatic overclocking if there is low temperature in the processor core.
    • Adaptive Thermal Limit: Adjusting of the processor to maintain a user predefined temperature.
  • Encryption: Includes the VIA PadLock engine
    • Hardware support for AES encryption, secure hash algorithm SHA-1 and SHA-256 and Random Number Generation

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