Successive Approximation ADC - Charge-redistribution Successive Approximation ADC

Charge-redistribution Successive Approximation ADC

One of the most common implementations of the successive approximation ADC, the charge-redistribution successive approximation ADC, uses a charge scaling DAC. The charge scaling DAC simply consists of an array of individually switched binary-weighted capacitors. The amount of charge upon each capacitor in the array is used to perform the aforementioned binary search in conjunction with a comparator internal to the DAC and the successive approximation register.

  1. First, the capacitor array is completely discharged to the offset voltage of the comparator, VOS. This step provides automatic offset cancellation(i.e. The offset voltage represents nothing but dead charge which can't be juggled by the capacitors).
  2. Next, all of the capacitors within the array are switched to the input signal, vIN. The capacitors now have a charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of them.
  3. In the third step, the capacitors are then switched so that this charge is applied across the comparator's input, creating a comparator input voltage equal to -vIN.
  4. Finally, the actual conversion process proceeds. First, the MSB capacitor is switched to VREF, which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now -vIN plus VREF/2. Subsequently, if vIN is greater than VREF/2 then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

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Charge-redistribution Successive Approximation ADC - Use With Non-ideal Analog Circuits
... an analog circuit - where the value of each successive bit is not perfectly 2^N (e.g. 1.1, 2.12, 4.05, 8.01, etc.) - a successive approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of ... the analog circuit used to implement a SAR ADC be very close to the ideal 2^N values otherwise, we cannot guarantee a best match search ...

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