Strain Engineering in CMOS Manufacturing
The use of various strain engineering techniques has been reported by many prominent microprocessor manufacturers, including AMD, IBM, and Intel, primarily with regards to sub-130 nm technologies. One key consideration in using strain engineering in CMOS technologies is that PMOS and NMOS respond differently to different types of strain. Specifically, PMOS performance is best served by applying compressive strain to the channel, whereas NMOS receives benefit from tensile strain. Many approaches to strain engineering induce strain locally, allowing both n-channel and p-channel strain to be modulated independently.
One prominent approach involves the use of a strain-inducing capping layer. CVD silicon nitride is a common choice for a strained capping layer, in that the magnitude and type of strain (e.g. tensile vs compressive) may be adjusted by modulating the deposition conditions, especially temperature. Standard lithography patterning techniques can be used to selectively deposit strain-inducing capping layers, to deposit a compressive film over only the PMOS, for example.
Capping layers are key to the Dual Stress Liner (DSL) approach reported by IBM-AMD. In the DSL process, standard patterning and lithography techniques are used to selectively deposit a tensile silicon nitride film over the NMOS and a compressive silicon nitride film over the PMOS.
A second prominent approach involves the use of a silicon-rich solid solution, especially silicon-germanium, to modulate channel strain. One manufacturing method involves epitaxial growth of silicon on top of a relaxed silicon-germanium underlayer. Tensile strain is induced in the silicon as the lattice of the silicon layer is stretched to mimic the larger lattice constant of the underlying silicon-germanium. Conversely, compressive strain could be induced by using a solid solution with a smaller lattice constant, such as silicon-carbon. See, e.g., U.S. Patent No. 7,023,018. Another closely related method involves replacing the source and drain region of a MOSFET with silicon-germanium.
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