Spansion - Products

Products

Spansion's product portfolio offers densities ranging from one-megabit to two-gigabits and an array of interfaces and features. It has developed two Flash memory technologies, single-bit-per-cell floating gate technology and one-, two- or more-bit-per-cell MirrorBit technology, with MirrorBit products based on two-bits per cell and allow offering a range of product configurations. The Company's products are designed for code storage and execution is based on NOR Flash memory architecture and utilize either traditional floating gate technology or its MirrorBit technology.

Spansion concentrates on the embedded electronics market and portions of the wireless handset market. Its Floating Gate and MirrorBit technology is used to make networking and telecommunications equipment, consumer electronics, gaming equipment, TV set-top control boxes, automotive equipment and personal computer peripherals. MirrorBit Technology represents nearly one fourth of the entire NOR flash memory market.

The company’s products offer designers the option to choose from 5V, 3V and 1.8V products that range from 1Mb to 2Gb.

Spansion’s standard parallel NOR flash includes Spansion’s MirrorBit NOR GL family of 3V flash memory. The product operates at 3.0 volts (Vcc), feature a random read speed of 90-100 nanoseconds (ns) access and offer a page read speed of 25 ns via an 8-word page buffer.

Spansion’s serial peripheral interface (SPI) devices read information serially, or one bit at a time, requiring fewer connections and pins, allowing for lower costs and simplified board layouts. Serial Flash memory is used in applications such as high-end printers, FPGAs, networking equipment and set-top boxes.

The MirrorBit SPI FL family of serial flash memory: Densities for the MirrorBit SPI Flash memory devices range from 4 Mb to 256 Mb with uniform 64 Kb sectors, and 4 Mb with parameter sectors. The 128 Mb device also features an optional 256 Kb sector architecture.

In August 2011, Spansion also announced that it had created the first single-die, 4-gigabit NOR product implemented at the 65-nm node.

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