PDP-11 Architecture - Instruction Set - Single-operand Instructions

Single-operand Instructions

The high-order nine bits specify the operation to be performed (with bit 15 generally selecting word versus byte addressing). (There are not as many operations as it seems, as most combinations of the high-order four bits are taken by the double-operand instructions.) A single group of six bits specifies mode and register, as defined above, for the single operand.

15 11 10 6 5 3 2 0
B 0 0 0 1 Opcode Mode Register
Opcode Mnemonic Effect
0003 SWAB Swap bytes: rotate 8 bits
004r (Jump to subroutine)
104x (Emulator trap)
0050 CLR Clear: dest = 0
1050 CLRB
0051 COM Complement: dest = ~dest
1051 COMB
0052 INC Increment: dest += 1
1052 INCB
0053 DEC Decrement: dest −= 1
1053 DECB
0054 NEG Negate: dest = −dest
1054 NEGB
0055 ADC Add carry: dest += C
1055 ADCB
0056 SBC Subtract carry: dest −= C
1056 SBCB
0057 TST Test: Load src, set flags only
1057 TSTB
0060 ROR Rotate right 1 bit
1060 RORB
0061 ROL Rotate left 1 bit
1061 ROLB
0062 ASR Shift right: dest >>= 1
1062 ASRB
0063 ASL Shift left: dest <<= 1
1063 ASLB
0064 MARK Return from subroutine, skip 0..63 instruction words
1064 MTPS Move to status: PS = src
0065 MFPI Move from previous I space: −(SP) = src
1065 MFPD Move from previous D space: −(SP) = src
0066 MTPI Move to previous I space: dest = (SP)+
1066 MTPD Move to previous D space: dest = (SP)+
0067 SXT Sign extend: dest = (16 copies of N flag)
1067 MFPS Move from status: dest = PS


The SWAB instruction—which swaps the high-order and low-order byte of the specified word—does not have two variations for byte- and word-addressing.

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