The semiconductor industry is trying to make 3-D chips for decades now. Why? Because light travels on shorter distances, leading to faster and smaller circuits. But nobody was really successful. (Check here or there for example.)
Now it seems that researchers at the Rensselaer Polytechnic Institute (RPI) have developed a new interconnect technology which might deliver electronic circuits functioning in three dimensions.
Researchers at Rensselaer’s Focus Center-NY for Interconnections for Gigascale Integration believe that a strategy in which several chip wafers are bonded together in 3-D and interconnected provides an effective means to integrate chip technologies.
"At Rensselaer, we’re working with others to develop a very promising approach to building vertically integrated (3D) circuits; going up instead of across", says Jian-Qiang "James" Lu, a research associate professor of physics.
Here is the technical explanation.
To make and interconnect 3-D chips, Lu explains Rensselaer’s process of effectively bonding wafers together face-to-face. After bonding and thinning the top wafer, inter-wafer interconnects are formed using the industry standard "damascene" processing. This process includes drilling a hole using dry etching, filling it with copper (the industry standard material), and polishing away extra copper define the metal lines that will carry signals around the “stacked-chip” product.
Here is an image of a "processed Si wafer, supplied by SEMATECH, bonded to a glass wafer after the silicon was removed" (Credit: Russ Kraft).
So what's next? No real products are announced at this stage, but researchers are optimistic.
Further advancements and benefits of such a system on a 3-D chip are that each layer can be optimized for any given technology, meaning in one 3-D chip you could integrate (hyper-integrate) terahertz technology, mixed signal processing, wireless and optical systems.
Source: Rensselaer Polytechnic Institute (RPI) News release, August 29, 2003
1:59:56 PM
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